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During the last two weeks, including two full days at the EMC Analyst Summit, we have been educated (inundated) with information regarding the wonders of the coalition of VMware, Cisco and EMC to produce a series of integrated products that include unified computing (Cisco), virtualized operating systems (VMware) and integrated storage (EMC) called Vblocks.
The strategy of the Virtual Computing Environment (VCE) coalition is to create a pre-emptive product offering that trumps the integrated products of IBM, HP and Oracle-Sun. EMC CEO Joe Tucci’s clearly stated position, reinforced by his cadre is that POWER, SPARC and Itanium processors are going to be relegated to buggy whip status in the next wave of technology. Tucci established a baseline of technology waves going back to our mutual youth, starting with the mainframe, followed by the minicomputer, PCs and by network distributed computing and culminating in wave next, which will be dominated by x86 silicon, unified computing, virtualized infrastructure and liquid pools of combined resources.
Easily impressed as I am, I can’t quite swallow the quiet demise of everything other than x86, despite the fact that that many of us predicted the same about twenty-five years ago. But just for now I’ll play along.
In the next generation, if indeed ‘the cloud’ is really real and the vision of VCE prevails, the real new winners are going to be the old winners.Intel and telcos such as AT&T are the silent partners in all things touted as futures at EMC’s Analyst Summit. And in many ways, they should be. Telco invested in the infrastructure in the late 90s, and they own a huge amount of dark fiber, with component suppliers such as Adva Optical ready to supply all the connecting and switching gear at new and reasonable cost levels. And, Intel has continued to pour billions into research and fab development against a scenario of decreasing volumes dictated by multi-core processors and virtualization allowing a one-to-ten (or more) server to virtual server ratio.
Of course, execution is really tough to pull off in a well-managed company, let alone a coalition. And the coalition is dependent on a new venture (currently called Acadia) for much of the delivery mechanism necessary to take the market share of Cisco blades from noise level to potentially dominant technology. Now that is going to be a tough act. And, HP has already fired off a first salvo with its own unified computing arsenal, and you know that IBM and Oracle-Sun are not going to shuffle off to obscurity. In fact, all have pre-emptive products of their own.
By James E. Bagley, senior analyst
Storage strategies NOW
Software-based features usually don’t match general availability of the hardware that runs them. The reason is quite simple. In most cases, final software testing can’t happen until the hardware is completely revved up. And the most advanced features often need those final tweaks at the hardware level for proofing. When faced with delaying an entire product introduction (often heavily pre-hyped) versus releasing the hardware and promising a free or low-cost upgrade on the advanced software feature, many organizations will opt for the latter, however fraught with peril.
Peril comes from two sides. The first side is the automatic overhang of the hardware revenue. Customers can often defer the hardware investment until all of the software features are available, reducing their risk and near term capital outlays. The second side of the peril is if, in the final round of testing, some kind of hardware non-starter is discovered that requires a hardware replacement to make that software feature work. Man, I’ve been there before.
Even if the best plans work out, software upgrades are not free, even if there is no cost from the vendor. Doing brain surgery on modern equipment has its own set of risks. Minimally, the product needs to be taken out of service at some point in the process. Maximally, an engineer needs to walk through a tedious process that can produce disaster by a single error while the data center manager sweats and fumes.
As hardware manufacturers increasingly rely on sophistication in operating software for product differentiation, this dilemma will haunt more and more product developers and marketers. The worst cases are when the feature delay has not been planned into the launch cycle, causing the product marketing team to invent ‘benefits,’ often associated with reduced margins, for a buy the hardware now and add the software features at a later date. Since this is a fact of life, and most companies will opt for near term hardware revenue and market share, this modern equivalent of ‘damn the torpedoes, full speed ahead’ is likely to be the norm.
Every meeting regarding Solid State memory technology includes pre-emptive prognostications about future technology. Phase Change Memory is always included as an alternative to adoption of the current state-of-the-industry NAND FLASH systems. We recently had the opportunity to discuss this really cool (or hot, depending on your perspective) technology with Cliff Smith and Mark Miller of Numonyx, a silicon fabricator with a huge investment in all forms of solid state memory technologies.
In a nutshell, Phase Change Memory is based on a radical approach to ‘remembering’ – one that involves no electrons – just a physical change in the substrate material that yields a closed or open circuit. What could be simpler? The devil in the detail involves a physical change in the actual substrate. That is, heat it up and cool it down at a varying rate. Cool it fast equals a one, cool it slow equals a zero (or vice-versa). Literally, PCM involves smelting the substrate on the fly. While the technology is in its infancy, it will certainly be a primary contender for memory systems in the next ten years. The primary advantage of PCM is that, like DRAM, individual bits can be read or written without the erase-write cycle involved in NAND FLASH. There are several disadvantages, including temperature limitations (don’t store the device at temperatures above 85c for long periods), but they are relatively small compared with the well-discussed NAND issues of wear-leveling, write amplification, and endurance.
So why are all the smart guys developing NAND FLASH SSD’s? The answer is simple. On the current Moore’s Law flight plan, it will be about a decade before PCM’s can compete on a cost-per-bit basis. DRAMs, on the other hand, will be in jeopardy in five or six years. And remember, PCM’s are non-volatile with power disruptions.
We analyze all forms of Solid State memory in context with enterprise and portable applications. In our current assessment, NAND FLASH will remain the pre-dominant technology for at least the next five years. But planning new systems beyond that point will certainly involve a PCM strategy.–Jim Bagley
In recent briefings with solid state drive (SSD) component and appliance manufacturers, there remains a significant divide between strategies aimed at dealing with the problem, within NAND flash, generally referred to as ‘write amplification.’ NAND devices require an entire block to be erased and re-written, even if only one byte is updated. Since this is a time-consuming process, and SSD’s are built for speed, two basic strategies exist in order to deal with the problem.
The first strategy has to do with using high speed (and expensive) volatile DRAM memory in order to buffer the write. This method is used in many hard disk drive RAID controllers as well. It means that the writes are captured into staging blocks and only written after the block is full or an algorithmically determined amount of time has passed. This saves time for many applications such as on-line transaction processing and streaming data input, such as video surveillance, but it does imply additional costs, not just for the volatile memory, but for a means to protect it. Protection is provided by an Uninterruptible Power Supply (UPS) for an entire system or data center, a battery for the local memory circuit or a ‘super capacitor’ which will keep the memory alive until it can be written to the non-volatile media (be it HDD or FLASH).
The second strategy gets more complex from an algorithm and provisioning standpoint, but has the advantages of cost savings and eliminates maintenance issues associated with UPS and battery systems. While all processes lie beneath the surface of the controller algorithm, and the details of the actually algorithm are closely guarded and often involved in patents, they all generally involving keeping spare areas erased and ready to write the ‘staging’ data into, and some sort of background clean-up algorithm, not unlike an HDD ‘defragmenter’ that goes through and frees the staged blocks that may only contain a fractional amount of new data. While this process may be slower than the buffering method in many application scenarios, since SSDs are already an order of magnitude faster than HDDs it is often very acceptable and has an additional advantage when employed within an overall wear-leveling and endurance management process.
The two strategies are exemplified by two appliance integrations of which we are very familiar. The WhipTail Technologies appliance uses DRAM buffering in an SSD-only array with a UPS built into its 1.5-, 3- or 6TB appliance. Atrato, on the other hand, uses SSDs as a FIFO cache and an algorithm that analyzes the application’s usage of the data to determine whether to finally place the data on SSD or HDD, both of which are available within the its storage system and can be built with varying capacities of each. WhipTail has the bandwidth advantage, but is expensive. Atrato has a cost advantage and total storage advantage as well. Both are positioned to take advantage better and faster SSD as coming on the market in 3.5-inch and 2.5-inch form factors.
The different strategies and performance results demand a common method of benchmarking, so we continue to encourage all contenders to join the Storage Performance Council benchmarks.–Jim Bagley